Design a signed fixed-point adder with saturation arithmetic.

Module name: fp_add
Parameters:
  - WIDTH = 24        // Total bit width
  - FRAC  = 8         // Fractional bits (integer bits = WIDTH - FRAC - 1 sign bit)

Ports:
  - input  signed [WIDTH-1:0] a       // First operand in Q(WIDTH-FRAC-1).FRAC format
  - input  signed [WIDTH-1:0] b       // Second operand
  - output signed [WIDTH-1:0] sum     // Saturated sum
  - output                    overflow // High when saturation occurred

Functional specification:
  - Compute a + b in fixed-point representation
  - If the result overflows (exceeds the maximum positive value), saturate to the maximum positive value: {1'b0, {(WIDTH-1){1'b1}}}
  - If the result underflows (below the minimum negative value), saturate to the minimum negative value: {1'b1, {(WIDTH-1){1'b0}}}
  - The overflow flag should be asserted when saturation occurs
  - This is a purely combinational module (no clock or reset)

Example (WIDTH=24, FRAC=8):
  - Representable range: approximately -32768.0 to +32767.99609375
  - a = 24'h007F80 (127.5), b = 24'h007F80 (127.5) → sum = 24'h00FF00 (255.0), overflow = 0
  - a = 24'h7FFF00 (max positive), b = 24'h000100 (1.0) → sum = 24'h7FFFFF (saturated max), overflow = 1
