Design a pipelined signed fixed-point divider.

Module name: fp_div
Parameters:
  - WIDTH = 24        // Total bit width
  - FRAC  = 8         // Fractional bits

Ports:
  - input                       clk
  - input                       rst_n       // Active-low synchronous reset
  - input  signed [WIDTH-1:0]   dividend
  - input  signed [WIDTH-1:0]   divisor
  - input                       valid_in    // Asserts for one cycle with new operands
  - output signed [WIDTH-1:0]   quotient    // Fixed-point quotient
  - output                      valid_out   // Asserts for one cycle when result is ready
  - output                      div_by_zero // Asserts with valid_out if divisor was zero

Functional specification:
  - Divide dividend by divisor (both Q(WIDTH-FRAC-1).FRAC signed fixed-point)
  - Uses iterative non-restoring division over multiple clock cycles
  - valid_in pulse latches operands and starts computation
  - valid_out asserts for one cycle when the quotient is ready
  - div_by_zero asserts alongside valid_out if the original divisor was zero
  - When div_by_zero is asserted, quotient output is undefined
  - Sequential (clocked, pipelined/iterative)
