Design a simple UDP packet parser for network packet processing.

UDP (User Datagram Protocol) is the transport layer protocol commonly used in
financial market data feeds due to its low latency. This module parses a
simplified UDP packet where bytes arrive sequentially.

Module name: udp_rx
Ports:
  - input        clk
  - input        rst_n
  - input  [7:0] data_in        // Input byte from packet stream
  - input        data_valid     // Input byte is valid
  - input        data_last      // Marks the final byte of the packet
  - output [15:0] src_port      // Source port extracted from header
  - output [15:0] dst_port      // Destination port extracted from header
  - output [15:0] udp_length    // UDP length field from header
  - output [7:0]  payload_data  // Payload byte pass-through
  - output        payload_valid // Asserted when payload_data is valid
  - output        pkt_done      // Pulses for one cycle when packet is complete
  - output        error         // Asserted if packet is malformed

Functional specification:
  - Bytes arrive one per clock cycle when data_valid is high
  - The first 8 bytes form the UDP header:
      Byte 0-1: Source port (big-endian)
      Byte 2-3: Destination port (big-endian)
      Byte 4-5: UDP length (big-endian)
      Byte 6-7: Checksum (ignored, not stored)
  - After the 8-byte header, remaining bytes are payload
  - Payload bytes are output on payload_data with payload_valid=1
  - data_last marks the final byte of the packet
  - When data_last is received, pkt_done pulses high for one cycle
  - If data_last asserts before all 8 header bytes are received, error pulses
  - After pkt_done or error, the parser resets for the next packet
  - Header fields (src_port, dst_port, udp_length) are registered outputs that
    become valid when the header is fully parsed and remain valid until next packet

Example:
  - 10-byte packet: [00,50, 1F,90, 00,0A, 00,00, DE,AD]
    src_port=0x0050(80), dst_port=0x1F90(8080), length=10
    payload bytes: 0xDE, 0xAD with payload_valid=1
